`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:51:24 08/31/2014
// Design Name:   ecc_correction
// Module Name:   E:/Xilinx/Examples/ppc_no_cache/pcores/xps_mch_emc_v3_01_a/hdl/verilog/testbench.v
// Project Name:  ecc
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ecc_correction
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module testbench;

	// Inputs
	reg [31:0] data;
	reg [7:0] ecc_code;

	// Outputs
	wire [31:0] data_corrected;

	// Instantiate the Unit Under Test (UUT)
	ecc_correction uut (
		.data(data), 
		.ecc_code(ecc_code), 
		.data_corrected(data_corrected)
	);

	initial begin
		// Initialize Inputs
		data = 0;
		ecc_code = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		data = 123464;
		ecc_code = 51;
		
		#10;
		data = 122240;
		ecc_code = 23;
		
		#10;
		data = 4546282;
		ecc_code = 62;
		
		#10;
		data = 4532458;
		ecc_code = 52;

	end
      
endmodule

